wire cs;
/* Output signals from can_btl module */
wire clk_en;
wire sample_point;
wire sampled_bit;
wire sampled_bit_q;
wire tx_point;
wire hard_sync;
wire resync;
/* output from can_bsp module */
wire rx_idle;
wire transmitting;
wire last_bit_of_inter;
wire set_reset_mode;
wire node_bus_off;
wire error_status;
wire [7:0] rx_err_cnt;
wire [7:0] tx_err_cnt;
wire rx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
wire tx_err_cnt_dummy; // The MSB is not displayed. It is just used for easier calculation (no counter overflow).
wire transmit_status;
wire receive_status;
wire tx_successful;
wire need_to_tx;
wire overrun;
wire info_empty;
wire set_bus_error_irq;
wire set_arbitration_lost_irq;
wire [4:0] arbitration_lost_capture;
wire node_error_passive;
wire node_error_active;
wire [6:0] rx_message_counter;
wire tx_out;
wire tx_oen;
wire rst;
wire we;
wire [7:0] addr;
wire [7:0] data_in;
reg [7:0] data_out;
/* Connecting can_registers module */
can_registers i_can_registers
(
.clk(clk_i),
.rst(rst),
.cs(cs),
.we(we),
.addr(addr),
.data_in(data_in),
.data_out(data_out_regs),
.irq(irq_o),
.sample_point(sample_point),
.transmitting(transmitting),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt(rx_err_cnt),
.tx_err_cnt(tx_err_cnt),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
/* Mode register */
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
/* Command register */
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(abort_tx),
.tx_request(tx_request),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
/* Arbitration Lost Capture Register */
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
/* Error Code Capture Register */
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
/* Bus Timing 1 register */
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
/* Error Warning Limit register */
.error_warning_limit(error_warning_limit),
/* Rx Error Counter register */
.we_rx_err_cnt(we_rx_err_cnt),
/* Tx Error Counter register */
.we_tx_err_cnt(we_tx_err_cnt),
/* Clock Divider register */
.extended_mode(extended_mode),
.clkout(clkout_o),
/* This section is for BASIC and EXTENDED mode */
/* Acceptance code register */
.acceptance_code_0(acceptance_code_0),
/* Acceptance mask register */
.acceptance_mask_0(acceptance_mask_0),
/* End: This section is for BASIC and EXTENDED mode */
/* This section is for EXTENDED mode */
/* Acceptance code register */
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
/* Acceptance mask register */
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
/* End: This section is for EXTENDED mode */
/* Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data */
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12)
/* End: Tx data registers */
);
assign irq_on = ~irq_o;
/* Connecting can_btl module */
can_btl i_can_btl
(
.clk(clk_i),
.rst(rst),
.rx(rx_i),
/* Mode register */
.reset_mode(reset_mode),
/* Bus Timing 0 register */
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
/* Bus Timing 1 register */
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
/* Output signals from this module */
.clk_en(clk_en),
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.resync(resync),
/* output from can_bsp module */
.rx_idle(rx_idle),
.transmitting(transmitting),
.last_bit_of_inter(last_bit_of_inter)
);
can_bsp i_can_bsp
(
.clk(clk_i),
.rst(rst),
/* From btl module */
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.addr(addr),
.data_in(data_in),
.data_out(data_out_fifo),
.fifo_selected(data_out_fifo_selected),
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