8051 pdf datasheet

80C51 ARCHITECTURE
MEMORY ORGANIZATION
All 80C51 devices have separate address spaces for program and
data memory, as shown in Figures 1 and 2. The logical separation of
program and data memory allows the data memory to be accessed
by 8-bit addresses, which can be quickly stored and manipulated by
an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also
be generated through the DPTR register.
Program memory (ROM, EPROM) can only be read, not written to.
There can be up to 64k bytes of program memory. In the 80C51, the
lowest 4k bytes of program are on-chip. In the ROMless versions, all
program memory is external. The read strobe for external program
memory is the PSEN (program store enable).
Data Memory (RAM) occupies a separate address space from
Program Memory. In the 80C51, the lowest 128 bytes of data
memory are on-chip. Up to 64k bytes of external RAM can be
addressed in the external Data Memory space. In the ROMless
version, the lowest 128 bytes are on-chip. The CPU generates read
and write signals, RD and WR, as needed during external Data
Memory accesses.
External Program Memory and external Data Memory may be
combined if desired by applying the RD and PSEN signals to the
inputs of an AND gate and using the output of the gate as the read
strobe to the external Program/Data memory.