PSRR技术(2) - 详解稳压电路的PSRR技术

因此，其实作者君拿到的LDO并不是用红色的Cc0来做compensation的，而是加上了蓝色的Cc和绿色的C1。这样一看，OTA的output node（或者说是输出级的power pmos的gate）并没有通过capacitor连接起来。而是，跨过了一个common gate的nmos，Cc才连着output那里。

然后，作者君就找到了这个传说中的著名AHUJA compensation的paper：An Improved Frequency Compensation Technique for CMOS Operational Amplifiers， BHUPENDRA K. AHUJA， IEEE JOURNAL OF SOLID-STATE CIRCUITS， VOL. SC-18，NO. 6， DECEMBER 1983， p629

不好意思，抄一点paper的原文，因为本人觉得自己写的不会更好……

这个传统的miller compensation的问题有两个：

无法驱动很大的电容负载：The op amp stability is severely degraded for capacitive loads of the same order as compensation capacitor （CL must be less than gM2CC/g~l to avoid second pole crossover of the unity gain frequency）。

当power mos是nmos的时候，miller造成的zero会严重影响PSRR的性能：In case of p-channel MOS transistors for the input differential stage， the negative power supply displays a zero at the dominant pole frequency of the op amp in unity gain configuration. This results in serious performance degradation for sampled data systems which use high-frequency switching regulators to generate their power supplies. （In the case of n-channel MOS transistors for the input differential pair， it is the positive supply which shows similar degradation.） This is illustrated in Fig. l（d）。

然后，这个compensation的idea就是除去这个可以short第一级output和第二级output。下面的内容大家不想看可以略去。

The technique is based on removing the feed forwardpath from the first stage output to the op amp output. The circuit shown in Fig. 1 has a current CCd（V. – Vl）/dt flowing into the first-stage output. If one can devise a circuit where only CCdVO/dt current flows into the first stage output， one would have eliminated the feedforward path while still producing a dominant pole due to the Miller effect. The only difference is that Miller capacitance is now AICCrather than （1+ AZ） CCwhere A~is the secondstage voltage gain. Thus， the conceptual ac equivalent of such a circuit is shown in Fig. 2（a）。 Here the compensation capacitor is shown to be connected between the output node and a virtual ground （or ac ground）， while the controlled current source having the same value as CCdVo/dt charges the first-stage output. It can be shown that for such an arrangement， the open-loop gain of the op amp is given by

where Al = g~l RI = dc gain of the first stage and A2 = gm2Rz = clc gain of the second stage.

Fig. 2（b） shows its pole-zero location. Notice that there is no finite zero in this circuit and that both the poles are real and are widely spaced.

Assuming the internal node capacitance Cl being much smaller than the compensation capacitor CCor the load capacitance CL， the unity gain frequency WI is still given by g~l/CC. This results in

Taking some typical design values of a two-stage amplifier as given by

it can drive up to 100pF load cap.

another advantage is：

which indicates that is has the same poles as the open-loop gain and a zero which is created by the parasitic capacitance at the first-stage output. Thus， in a unity gain configuration， the VBB PSRR is given by