FETMX8MM-C 核心板基于NXP 公司的i.MX8M Mini 四核64位处理器设计,主频最高1.8GHz,ARM Cortex-A53架构;2GB DDR4 RAM,支持一个通用型Cortex®-M4 400 MHz内核处理器。可提供多种音频接口,包括I2S、AC97、TDM、PDM和SPDIF。提供多种外设接口,如MIPI-CSI、MIPI-DSI、USB、PCIe、UART、eCSPI、IIC和千兆以太网。
目标应用:
·IP摄像头视频监控 ·双向视频会议
·可视门铃·图像分析
·音频处理·音频广播系统
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Cortex A53 Core:
• 4x Cortex-A53 processors
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• Target frequency of 1.8GHz
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• Support of 64-bit Armv8-A architecture
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• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture
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• 32 KB L1 Instruction Cache
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• 32 KB L1 Data Cache
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• 512 KB unified L2 cache
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Cortex M4 Core:
• 1x Cortex-M4 processor
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•frequency of 400MHz
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• 256 KB tightly coupled memory (TCM,128 KB TCMU, 128 KB TCML)
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• 2GB
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• DDR4
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• 8GB
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• eMMC Flash
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LCDIF Display Controller:
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• Support up to 2 layers of overlay
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• Support up to 1080p60 display through MIPI DSI
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MIPI Interface:
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• 4-lane MIPI CSI interface,operating up to a maximum bit rate of 1.5 Gbps.
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• 4-lane MIPI DSI interface,operating up to a maximum bit rate of 1.5 Gbps.
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Audio:
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• SPDIF input and output, including a new Raw Capture input mode
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•Five synchronous audio interface (SAI) modules supporting I2S,AC97, TDM,codec/DSP,and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one SAI with 4 Tx and 4 Rx lanes,two SAI with 2 Tx and 2 Rx lanes,and one SAI with 1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.
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• 8-Channel Pulse Density Modulation (PDM) input
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3D GPU Core:
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• GCNanoUltra
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• Support OpenGL ES 1.1, 2.0
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• Support OpenVG 1.1
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• TrustZone support using a local MMU to manage secure regions
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2D GPU Core:
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• GC320
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• Support multi-source composition
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• Support one-pass filter
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Decoder:
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• 1080p60 VP9 Profile 0, 2 (10-bit)
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• 1080p60 HEVC/H.265 Decoder
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• 1080p60 AVC/H.264 Baseline, Main, High decoder
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• 1080p60 VP8
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Encoder:
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• 1080p60 AVC/H.264 Encoder
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• 1080p60 VP8
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One PCI Express (PCIe)
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• Single lane supporting PCIe Gen2
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• Dual mode operation to function as root complex or endpoint
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• Integrated PHY interface
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• Support L1 low power sub-state
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Two USB 2.0 OTG controllers with integrated PHY interfaces
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Two Ultra Secure Digital Host Controller (uSDHC) interfaces:
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• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100MB/sec
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• Support for SDXC (extended capacity)
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• 1.8 V and 3.3 V operation, but do not support 1.2V operation.
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One Gigabit Ethernet controller:
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• support for Energy Efficient Ethernet (EEE)
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• Ethernet AVB,
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• IEEE 1588
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Four Universal Asynchronous Receiver/Transmitter (UART) modules:
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• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,odd, or none)
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• Programmable baud rates up to 4 Mbps.
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• 32-byte FIFO on Tx and 32half-word FIFO on Rx supporting auto-baud
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Four I2C modules:
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I2C provides serial interface for external devices. Data rates of up to 320 kbps are supported.
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Three eCSPI modules:
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Full-duplex enhanced Synchronous Serial Interface, with data rate up to 52 Mbit/s. Configurable to support Master/Slave modes, four chip selects to support multiple peripherals.
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The FlexSPI module acts s an interface to external serial flash devices. This module contains the following features:
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• Flexible sequence engine to support various flash vendor devices
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• Single pad/Dual pad/Quad pad mode of operation
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• Single Data Rate/Double Data Rate mode of operation
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• Parallel Flash mode
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• DMA support
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• Memory mapped read access to connected flash devices
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• Multi master access with priority and flexible and configurable buffer for each master
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