有些应用中,需要降低Xilinx MPSoC的功耗。缺省设置中,R5/GPU都被使能。如果需要省电,可以在Vivado里关闭R5/GPU。步骤如下:
1.选中 MPSoC IP,在右键菜单中选择Block Properties.
2.在窗口Block Properties中,选择Properties.
3. 在窗口中,展开 “Config”.
4. 在搜索框中输入 “Power”, 出现PSU_RPU_POWER_ON等选项。如果值是1,表示被使能;如果值是0,表示被关闭。如果要关闭,点击最左边的编辑图标,输入0。
编辑前Power选项
编辑后Power选项
在Vivado里编辑完成后,执行“Generate Output Products”, 在导出Hardware的HDF/XSA文件。
2. JTAG检查R5/A53状态
在SDK/Vitis里创建FSBL和Standalone程序,启动后,在XSCT命令后窗口下,检查R5/A53状态,可以看到设置为0的R5/A53的状态是No Power。
xsct% connect
tcfchan#2
xsct% target
1 PS TAP
2 PMU
3 PL
4 PSU
5 RPU (Reset)
6 Cortex-R5 #0 (No Power)
7 Cortex-R5 #1 (No Power)
8 APU
9 Cortex-A53 #0 (Running)
10 Cortex-A53 #1 (Power On Reset)
11 Cortex-A53 #2 (No Power)
12 Cortex-A53 #3 (No Power)
3. 代码
代码在psu_init.c里的函数psu_peripherals_powerdwn_data( )里。
/*
POWER DOWN REQUEST INTERRUPT ENABLE
/
/
Register : REQ_PWRDWN_INT_EN @ 0XFFD80218
Power-down Request Interrupt Enable for Dual_R5
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_RPU 1
Power-down Request Interrupt Enable for GPU PP0
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP0 1
Power-down Request Interrupt Enable for GPU PP1
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_PP1 1
Power-down Request Interrupt Enable for ACPU2
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU2 1
Power-down Request Interrupt Enable for ACPU3
PSU_PMU_GLOBAL_REQ_PWRDWN_INT_EN_ACPU3 1
Power-down Request Interrupt Enable Register. Writing a 1 to this locati
on will unmask the Interrupt.
(OFFSET, MASK, VALUE) (0XFFD80218, 0x0000043CU ,0x0000043CU)
/
PSU_Mask_Write(PMU_GLOBAL_REQ_PWRDWN_INT_EN_OFFSET,
0x0000043CU, 0x0000043CU);
/##################################################################### */
/*
POWER DOWN TRIGGER
/
/
Register : REQ_PWRDWN_TRIG @ 0XFFD80220
Power-down Request Trigger for Dual_R5
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_RPU 1
Power-down Request Trigger for GPU PP0
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_PP0 1
Power-down Request Trigger for GPU PP1
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_PP1 1
Power-down Request Trigger for ACPU2
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU2 1
Power-down Request Trigger for ACPU3
PSU_PMU_GLOBAL_REQ_PWRDWN_TRIG_ACPU3 1
Power-down Request Trigger Register. Writing a 1 to this location will t
rigger a power-down request to the PMU.
(OFFSET, MASK, VALUE) (0XFFD80220, 0x0000043CU ,0x0000043CU)
/
PSU_Mask_Write(PMU_GLOBAL_REQ_PWRDWN_TRIG_OFFSET,
0x0000043CU, 0x0000043CU);
/##################################################################### */
审核编辑 :李倩
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原文标题:【干货分享】 在Vivado里关闭R5/GPU,降低Xilinx MPSoC的功耗
文章出处:【微信号:zhuyandz,微信公众号:FPGA之家】欢迎添加关注!文章转载请注明出处。
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