先给大家分享一个测试设计的职位描述:
Job Function: Definition, architecture, modeling, verification, bring-up, debug and support of structural test for achievement of high defect coverage of microprocessor designs from product definition through production.
Responsibilities:
• Define, model and verify DFT features.
• Utilize industry-standard ATPG tools to generate patterns and verify them.
• Simulate/verify DFT patterns using Verilog VCS.
• Bring-up and debug DFT patterns on the ATE.
• Develop, implement and support DFT methodologies.
• Proficient with at-speed scan architectures, memory BIST and/or logic BIST.
• Proficient with coding/scripting using Perl.
• Mentor less senior DFT engineers and lead their efforts in achieving project objectives.
• Collaborate with engineering professionals across the company in order to advance the state of the art of DFT and test practices at AMD.
Preferred Experience:
• Master of EE or above. 4+ years DFT experience.
• Experience in microprocessor design or experience in handling complex SOC designs.
• Knowledgeable about industrial standards in DFT such as LBIST/JTAG/MBIST.
• Knowledgeable about ATE testers and ATPG standard practices.
• Expert knowledge of Verilog, RTL, Verilog simulators and waveform debugging tools.
• Good debugging capability with both RTL and gate-level simulations.
• Good communication skills and the ability to work with geographically distributed design sites.
可以看出要求很多。一些刚进入电路行业的人会认为测试相关的事情技术含量很低啊,当然测试间的操作员是要做很多重复性劳动。但是测试设计完全是另一回事。大些的企业里,测试设计工程师跟测试工程师是2个不同职位。前者主要负责制定测试策略,添加测试电路,生成测试向量,协助后者调通测试程序。后者主要在机台上调通程序,处理量产中测试相关问题,分析失效原因,协助其他工艺提高良品率。小点的公司可能2件事情同一个人做,或者干脆由管综合的人做前者的事情,后者由工厂相关人员协助完成。由于大部分公司做的产品可靠性要求不高,所以很多时候只是在芯片上运行一下功能测试的程序,不需要做全面的扫描,对测试设计的专业性也就没那么高。另外很多公司甚至没有量产经历,导致真正水平较高的测试设计人员很难找到。一般来说做测试设计的人员都是有过一段时间逻辑电路设计经验的,测试工程师大部分是半导体厂直接招的毕业生练出来的。如果有公司要染指利润,可靠性要求较高的汽车电子,航空电子,最重要的是要有够水平的测试设计人员。
数字电路方面基本就这些岗位,模拟电路的岗位基本也就电路设计跟版图设计,一个电路公司里边如果有小妞,基本会出现在画版图的位置上,不过这些也基本是屌丝女,白富美基本不会光顾这种行业。下面看看这2种岗位的需求。
Position Description
Analog IC designer - responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.Background should demonstrate good problem solving skills, excellent analog aptitude, communication skills, and ability to work cooperatively in a team environment.The candidate would become part of analog IC design team creating leading edge IP (ADC's; DAC's; PLL's; SerDes) in leading edge processes (28nm and below).
Position Requirements
Must be familiar with design concepts for some basic analog functions including some of the following: data conversion, switched-capacitor circuits, op-amps, comparators, voltage and current references, phase-locked loops. Must be proficient in using CAD tools for circuit simulation, verification, and layout. 2-3 years employment or intern epxerience.Postion is also open to high performing recent EE graduate who has completed coursework that includes analog design.
版图工程师
Key Areas of Responsibility:
• Technical tasks involved are full customer layout design, layout check and verification.
Required knowledge, skills, abilities:
• Understanding the basic process and device knowledge. It is preferred to have knowledge on HV process/device.
• Familiar with layout tools, verification tools, command file based on cadence environment.
Additional knowledge, skills, abilities, certifications:
• Understanding basic IC design knowledge, especially in analog IC. Knowing of ESD and latch-up related will be considered a plus.
Required education and experience:
• At least Bachelor degree is required. More than one year of prior experience in full-custom –design analog IC layout is necessary. Layout experience in Power management IC with HV process is preferred.
现在画模拟版图电路基本都是cds的输入仿真工具,外加mentor的验证工具,现在模拟电路设计基本停留在cad阶段,eda还处在概念期,所以对人员经验要求较高。很多公司对有经验的电路工程师的定义是8年以上,可见这个岗位成才挺慢。做模拟电路需要对电路理论,半导体制程都有些了解,如果做高频电路,还要懂电磁波跟信号处理方面的东西,这些东西上大学期间不要说学生能够完全搞清楚的没几个,即使大部分教这些课程的叫兽僵尸,也只不过能把课本念熟练,真正完全理解的也不多见。所以真正有水平的模拟电路设计师,尤其是射频集成电路设计的,即使世界范围内也是稀缺资源。当然国内现在也有不少在做模拟电路的,但是大部分是做电源管理芯片,这个大概算模拟电路中的入门产品吧,甚至有些小公司直接翻抄版图,也能出些产品。整体来说,这个岗位属于需求大于供给的,即使水平一般,也不愁没地方工作,除非闹经济危机所有公司都裁员的时候。这个工作如果能把需要学的都完全搞明白了,其实劳动量也就是算一下电路参数,做个仿真,指导一下版图,属于所有岗位里最轻松的,不过想能搞明白电路各种参量的关系,也绝非易事。
画模拟版图的貌似跟电路设计正好相反,很多新招聘的版图员甚至不知道啥是三极管,然后被培训几天后就练习抄版图,然后熟练了逐渐自己设计。这个职位基本只要明白各层次之间关系,不是色盲,手脚够快,基本就能很快上手。不过这个职位也是所有职位里边最辛苦的,要看着花花绿绿的显示器不停的调整各个线条,而且版图设计时间压力一般也很大。一些私营公司的画图小妹甚至会被老板骂哭。这个职位可以说是最有屌丝气息的一岗位,当然如果熬出来收入也还不错,只是这个活计实在太费眼。
现在大部分电路都是数模混合,全芯片整合用数字设计流程,所以很多模拟电路设计都是设计模块,然后集成进芯片,由于模拟部分尚且没有标准的验证流程,也不能像数字电路那样放进fpga先跑跑看,而且模拟电路的测试设计也没有明确规范,所以集成在一起的芯片大部分问题是由于模拟电路部分。相信随着设计方法的改善与分工的细化,模拟电路方向会有更复杂的分工。
再来说说做数字后端版图的大概情况
Job Description:
· Interface with IC Design/Verification team (timing and power constraints definition)
· Writing, running, optimization of logic and physical synthesis scripts
· In-depth knowledge of STA.Ablility to handle timing analysis for multiple modes and corners
· Physical design Floor planning, place & route, clock tree synthesis, routing cleanup
· Power IR & EM analysis
· Parasitic extraction/SPEF/SDF generation
· Physical Verification (DRC, ERC, LVS, ANTENNA)
· Deep understanding of DSM effects (sub 65 nm experience preferred)
Requirements:
· Masters/Bachelor’s Degree in Electrical/Electronics Engineering or in related field
· Tool skills:
· Synopsys Design Compiler
· PERL, TCL languages
· Prime Time and constraint creation/modification
· IR analysis tool such as PrimeRail, Redhawk
· Synopsys ICC experience preferred
· Calibre
· Ability to speak and write English is a must, CET 6
· Self-motivated team player and able to work with minimum supervision
· Minimum 3 years of physical design and timing closure experience
· Willingness to take overseas business trip
以上是一个数字版图工程师的基本要求,现在大芯片后端综合基本都用ICC,也有用SOC encounter的,版图严重基本都是Calibre 这个工作除了要求熟练使用工具,掌握底层电路原理外,读懂工艺文件,很需要一些耐心与细致的性格,因为一般自动生成的版图未必能满足所有时序要求,而且会有一些drc错误,有时为了特殊目的也会做一些eco,这个就需要手工对版图进行一些编辑。面对满眼的连线,要逐一修改切保证没有失误,是对体力与脑力的双重考验。对这个工作岗位的要求其实也蛮高,不过由于其中一些杂活很耗费体力,所以一般公司也会找新人帮忙做后端的打杂工,然后逐渐学习成长。由于此类工具license基本是整个ic设计环节中最贵的,所以能有机会做后端综合的人不太多,当然开的工资相对于逻辑设计也就属于比较高的,这就相对于飞行员的工资比卡车司机高一样。
当然一般做后端设计的除了某些公司招聘的应届生逐渐上手的,还有一些是做手工版图的后来转行干这个,因为这个职位相对于全手工画图,工作量还是小一些的,而且听上去更高级一点。一旦开始做这个东西,基本就没有什么其他相关职位可以转行去干了,做资深工程师是唯一选择。
再说说仿真验证工程师的要求
Job Description:
Create verification plans for both block level and SoC level verification
Create testbenches in SystemVerilog with OVM/UVM
Utilize advanced verification techniques
Write tools and scripts in Perl and other script languages to enhance the verification process
Qualifications:
Experience with SystemVerilog and OVM/UVM
Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys)
Experience with standard IP blocks and protocols such as Ethernet, TCP/IP, IPSec, iSCSI, DDR3, PCIe
Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
Experience with tools for regression management, configuration management and bug tracking
Good software skills in object oriented programming (OOP), C, C++, Perl, csh
Good problem solving
BS, MS or PhD in computer science or engineering
很久以前做数字电路的是没有专门的验证工程师的,甚至现在小点的公司,这个任务也由做数字逻辑的兼任。不过现在大部分项目都是整合ip,验证的工作量反而更大一些,所以专门分离出来这个岗位。现在主流趋势都是用SV的UVM,不过也有很多继承之前项目的要用specman,当然也有继续用verilog写验证平台的,整体来说这个工作更适合之前习惯写C++的人来做,对于习惯了RTL代码的人,需要些时间接受这些以前专门用在软件开发方面的思维方式。这个工作主要是设计验证平台,验证用列并协同逻辑设计人员查找错误。很多公司新招的毕业生都会先做几天验证测试,跑跑仿真,这说明这个工作是门槛比较低的,但是这个门槛低仅针对开发验证用列,设计一个高效方便的验证平台并不是很简单的事情,很多公司仍然沿用Verilog编写的验证环境,估计主要因为找不到人能搭建一个基于新方法学有效的验证环境。这个工作估计是电路设计岗位里边最接近码农的,当然也是需求人数最多的。这个岗位所开的工资,从毕业生的6,7k到大忽悠的20k以上,都是可能的,当然这个工作做成了领导,手下的人也是最多的。
电路公司里边其他职位,基本都是跟软件或者整个系统相关了,这里就先介绍这些吧。对于其他的,如果有人比较了解,欢迎补充。
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