- FPGA仿真篇_使用脚本命令来加速仿真

这个工程比较大，脚本运行时间稍微会长一些时间，有兴趣学习PCIE或者DMA的同学需要好好看PDF以及.v文件和仿真出来的波形，学习脚本的同学认真看xilixn官网给出的脚本的写法，你会受益匪浅。
3.常用脚本语言的解释
#切换到工作目录
cd F:/Projects/BeiJing/sim
vsim -novopt work.histogram_2d_new_tb

#结束仿真
quit -sim

#仿真video_cap模块 不优化
vsim -novopt work.video_cap_tb

##退出当前仿真
quit -sim
##仿真image_src模块 不优化
vsim -novopt work.image_src

##设置仿真时间分辨率
##vsim -t 1ps   -lib work image_src
##设置仿真时间分辨率
vsim -t 1ns   -lib work AES256_tb 

##添加顶层所有的信号
add wave *

radix hex ##16进制显示
radix unsigned ##10进制显示

##编译xilinx库 VHDL 
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vcomponents.vhd
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vpackage.vhd
vcom –work simprim d:Xilinx/VHDL/src/simprims/simprim_VITAL.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCOMP.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VPKG.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VITAL.vhd
vcom –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCFG4K.vhd
vcom –work xilinxcorelib d:Xilinx/VHDL/src/ XilinxCoreLib/*.vhd

##编译xilinx库 Verilog
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vcomponents.v
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_Vpackage.v
vlog –work simprim d:Xilinx/VHDL/src/simprims/simprim_VITAL.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCOMP.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VPKG.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VITAL.v
vlog –work unisim d:Xilinx/VHDL/src/unisims/unisim_VCFG4K.v
vlog –work xilinxcorelib d:Xilinx/VHDL/src/ XilinxCoreLib/*.v

#新建工程 

project new D:/work/test
project open test
project addfile test.vhd

project compileall

vsim -L lpm -L altera 

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FPGA仿真篇-使用脚本命令来加速仿真一