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OMAP3503 应用处理器

数据： OMAP3515/03 Applications Processor 数据表

描述

设备基于增强型OMAP 3架构。

OMAP 3架构旨在提供一流的视频，图像和图形处理足以支持以下内容：

流媒体视频
视频会议
高分辨率静止图像

该设备支持高级操作系统（HLOS），例如：

Linux®
Windows®CE
Android ™

此OMAP设备包括高性能移动产品所需的最先进的电源管理技术。

以下子系统是设备的一部分：

基于ARM Cortex-A8微处理器的微处理器单元（MPU）子系统
用于支持显示的3D图形加速的PowerVR SGX子系统（仅限OMAP35设备）
支持多种格式的相机图像信号处理器（ISP）和连接到各种图像传感器的接口选项

显示子系统具有多种并发图像处理功能，以及支持各种显示器的可编程接口。显示子系统还支持NTSC和PAL视频输出。

3级（L3）和4级（L4）互连，为多个启动器提供高带宽数据传输到内部和外部存储器控制器以及打开芯片外设

该器件还提供：

全面的电源和时钟管理方案，可实现高性能，低功耗运行，以及超低功耗待机功能。该器件还支持SmartReflex自适应电压控制。这种用于自动控制模块工作电压的电源管理技术可降低有功功耗。
使用封装上封装（POP）实现的存储器堆叠功能（仅限CBB和CBC封装）

OMAP35器件采用515引脚s-PBGA封装（CBB后缀），515引脚s-PBGA封装（CBC后缀）和423引脚s-PBGA封装（CUS后缀）。 CUS包中没有CBB和CBC包的某些功能。（有关封装差异，请参见表1-1）。

本数据手册介绍了OMAP35应用处理器的电气和机械规格。除非另有说明，否则本数据手册中的信息适用于OMAP35应用处理器的商用和扩展温度版本。本数据手册由以下部分组成：

第2节：端子描述：分配，电气特性，多路复用和功能描述
第3节：电气特性：电源域，工作条件，功耗和直流特性
第4节：时钟规范输入和输出时钟，DPLL和DLL
第5节：视频Dac规范
第6节：时序要求和开关特性
第7节：封装特性：可用封装的热特性，器件命名和机械数据

特性

OMAP3 Devices:
- OMAP™ 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM® Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- PowerVR® SGX™ Graphics Accelerator
  - Tile-Based Architecture Delivering up to 1 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with ARM9™
- Commercial and Extended Temperature Grades
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- -KB Instruction Cache (4-Way Set-Associative)
- -KB Data Cache (4-Way Set-Associative)
- -KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
External Memory Interfaces:
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
- One HDQ™/1-Wire® Interface
- UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex™ Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
5-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface
Packages:
1.8-V I/O and 3.0-V (MMC1 Only),

Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.