描述
TMS320C6745 /6747器件是一款基于TMS320C674x DSP内核的低功耗数字信号处理器。它的功耗显着低于TMS320C6000 DSP平台的其他成员。
TMS320C6745 /6747器件使原始设备制造商（OEM）和原始设计制造商（ODM）能够快速推出市场上的设备。高处理性能。
TMS320C6745 /6747 DSP内核采用基于缓存的两级架构。 1级程序高速缓存（L1P）是32 KB直接映射高速缓存，1级数据高速缓存（L1D）是32 KB双向组关联高速缓存。 2级程序高速缓存（L2P）由256 KB内存空间组成，在程序和数据空间之间共享。 L2内存可以配置为映射内存，缓存或两者的组合。虽然系统中的其他主机可以访问DSP L2，但是其他主机可以使用额外的128KB RAM共享内存（仅限TMS320C6747），而不会影响DSP性能。
外设集包括：带管理数据输入/输出（MDIO）模块的10/100 Mbps以太网MAC（EMAC）;两个I 2 C总线接口; 3个多通道音频串行端口（McASP），带有16/9串行器和FIFO缓冲器;两个64位通用定时器，每个都可配置（一个可配置为看门狗）;可配置的16位主机端口接口（HPI）[仅限TMS320C6747];多达8个16引脚的通用输入/输出（GPIO），具有可编程中断/事件生成模式，与其他外设复用; 3个UART接口（一个具有 RTS 和 CTS ）;三个增强型高分辨率脉冲宽度调制器（eHRPWM）外设;三个32位增强型捕获（eCAP）模块外设，可配置为3个捕获输入或3个辅助脉冲宽度调制器（APWM）输出;两个32位增强型正交编码脉冲（eQEP）外设;和2个外部存储器接口：用于较慢存储器或外设的异步和SDRAM外部存储器接口（EMIFA），以及用于SDRAM的高速存储器接口（EMIFB）。
以太网媒体访问控制器（EMAC）提供TMS320C6745 /6747器件与网络之间的高效接口。 EMAC支持10Base-T和100Base-TX，或半双工或全双工模式下的10 Mbps和100 Mbps。此外，MDIO接口可用于PHY配置。
丰富的外设集可以控制外部外围设备并与外部处理器通信。有关每个外围设备的详细信息，请参阅本文档后面的相关章节以及相关的外围设备参考指南。
特性
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Software Support
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TI DSP/BIOS
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Chip Support Library and DSP Library
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375- and 456-MHz TMS320C674x VLIW DSP
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C674x Instruction Set Features
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Superset of the C67x+ and C64x+ ISAs
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Up to 3648 MIPS and 2736 MFLOPS C674x
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Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
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8-Bit Overflow Protection
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Bit-Field Extract, Set, Clear
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Normalization, Saturation, Bit-Counting
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Compact 16-Bit Instructions
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C674x Two-Level Cache Memory Architecture
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32KB of L1P Program RAM/Cache
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32KB of L1D Data RAM/Cache
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256KB of L2 Unified Mapped RAM/Cache
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Flexible RAM/Cache Partition (L1 and L2)
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Enhanced Direct Memory Access Controller 3 (EDMA3):
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2 Transfer Controllers
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32 Independent DMA Channels
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8 Quick DMA Channels
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Programmable Transfer Burst Size
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TMS320C674x Fixed- and Floating-Point VLIW DSP Core
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Load-Store Architecture with Nonaligned Support
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64 General-Purpose Registers (32-Bit)
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Six ALU (32- and 40-Bit) Functional Units
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Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
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Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
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Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
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Two Multiply Functional Units
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Mixed-Precision IEEE Floating Point Multiply Supported up to:
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2 SP x SP -> SP Per Clock
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2 SP x SP -> DP Every Two Clocks
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2 SP x DP -> DP Every Three Clocks
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2 DP x DP -> DP Every Four Clocks
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Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
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Instruction Packing Reduces Code Size
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All Instructions Conditional
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Hardware Support for Modulo Loop
Operation
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Protected Mode Operation
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Exceptions Support for Error Detection and Program Redirection
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128KB of RAM Shared Memory (TMS320C6747 Only)
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3.3-V LVCMOS I/Os (Except for USB Interfaces)
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Two External Memory Interfaces:
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EMIFA
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NOR (8- or 16-Bit-Wide Data)
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NAND (8- or 16-Bit-Wide Data)
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16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
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EMIFB
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32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
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16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
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Three Configurable 16550-Type UART Modules:
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UART0 with Modem Control Signals
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Autoflow Control Signals (CTS, RTS) on UART0 Only
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16-Byte FIFO
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16x or 13x Oversampling Option
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LCD Controller (TMS320C6747 Only)
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Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
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Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
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Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
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One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
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Programmable Real-Time Unit Subsystem (PRUSS)
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Two Independent Programmable Realtime Unit (PRU) Cores
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32-Bit Load and Store RISC Architecture
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4KB of Instruction RAM per Core
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512 Bytes of Data RAM per Core
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PRUSS can be Disabled via Software to Save Power
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Standard Power-Management Mechanism
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Clock Gating
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Entire Subsystem Under a Single PSC Clock Gating Domain
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Dedicated Interrupt Controller
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Dedicated Switched Central Resource
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USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
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USB 2.0 OTG Port with Integrated PHY (USB0)
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USB 2.0 High- and Full-Speed Client (TMS320C6747)
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USB 2.0 Full-Speed Client (TMS320C6745)
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USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
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USB 2.0 Full- and Low-Speed Host (TMS320C6745)
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High-Speed Functionality Available on TMS320C6747 Device Only
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End Point 0 (Control)
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End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
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Three Multichannel Audio Serial Ports (McASPs):
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TMS320C6747 Supports 3 McASPs
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TMS320C6745 Supports 2 McASPs
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Six Clock Zones and 28 Serial Data Pins
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Supports TDM, I2S, and Similar Formats
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DIT-Capable (McASP2)
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FIFO Buffers for Transmit and Receive
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10/100 Mbps Ethernet MAC (EMAC):
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IEEE 802.3 Compliant (3.3-V I/O Only)
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RMII Media-Independent Interface
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Management Data I/O (MDIO) Module
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Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
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One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
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One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
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Three Enhanced Pulse Width Modulators (eHRPWMs):
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Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
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6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
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Dead-Band Generation
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PWM Chopping by High-Frequency Carrier
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Trip Zone Input
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Three 32-Bit Enhanced Capture (eCAP) Modules:
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Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
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Single-Shot Capture of up to Four Event Time-Stamps
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Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
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TMS320C6747 Device:
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256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
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TMS320C6745 Device:
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176-pin PowerPAD Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
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Commercial, Industrial, Extended, or Automotive Temperature
参数 与其它产品相比 音频处理器
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|
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DSP |
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DSP MHz (Max) |
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Arm CPU |
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Operating Systems |
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DRAM |
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On-Chip L2 Cache/RAM |
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Approx. Price (US$) |
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McASP |
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McBSP |
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USB |
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EMAC |
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Package Group |
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PCI/PCIe |
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I2C |
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UART (SCI) |
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DSP MMACS |
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Other Hardware Acceleration |
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|
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TMS320C6745 |
TMS320C6747 |
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1 C674x |
1 C674x |
375
456 |
375
456 |
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N/A |
|
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TI RTOS |
SYS/BIOS |
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SDRAM |
SDRAM |
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256 KB |
256 KB |
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10.17 | 1ku |
11.73 | 1ku |
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2 |
3 |
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0 |
0 |
|
1 |
2 |
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10/100 |
10/100 |
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HLQFP |
BGA |
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N/A |
|
|
2 |
2 |
|
3 |
3 |
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3648 |
|
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PRU-ICSS |
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