LMK04610 LMK0461x 符合 JESD204B 标准的超低噪声和低功耗时钟抖动消除器

描述The LMK0461x device family is the industry’s highestperformance and lowest power jitter cleaner with JESD204B support.特性 Dual Loop PLL Architecture65-fs RMS Jitter (10 kHz to 20 MHz) 85-fs RMS Jitter (100 Hz to 20 MHz) –165-dBc/Hz Noise Floor at 122.88 MHzJESD204B SupportSingle Shot, Pulsed, and Continuous SYSREF10Differential Output Clocks in 8 Frequency GroupsProgrammable Output Swing Between 700 mVpp to 1600 mVppEach Output Pair Can be Configured to SYSREF ClockOutput16-Bit Channel DividerMinimum SYSREF Frequency of 25 kHz Maximum Output Frequency of 2 GHzPrecision Digital Delay, Dynamically AdjustableDigital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)60-ps Step Analog Delay 50% Duty Cycle Output Divides, 1 to 65535 (Even and Odd) 2 Reference InputsHoldover Mode, When Inputs are LostAutomatic and Manual Switch-Over ModesLoss-of-Signal (LOS) Detection 0.88-W Typical Power Consumption With 10 Outputs Active Operates Typically From a 1.8-V (Outputs, Inputs)and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)Fully Integrated Programmable Loop FilterPLL2PLL2 Phase Detector Rate Up to 250 MHzOSCin Frequency-DoublerIntegrated Low-Noise VCO Internal PowerConditioning: Better Than –80dBc PSRR on VDDOfor122.88-MHz Differential Outputs3- or 4-Wire SPIInterface (4-Wire is Default)–40ºC to +85ºC Industrial Ambient TemperatureSupports 105ºC PCB Temperature (Measured at Thermal Pad) LMK04610: 8-mm × 8-mm VQFN-56 Package With 0.5-mm Pitch All trademarks are the property of their respective owners.