| Number of channels (#) | 2 |
| Total supply voltage (Max) (+5V=5, +/-5V=10) | 15 |
| Total supply voltage (Min) (+5V=5, +/-5V=10) | 5 |
| Rail-to-rail | In to V-, Out |
| GBW (Typ) (MHz) | 0.35 |
| Slew rate (Typ) (V/us) | 0.11 |
| Vos (offset voltage @ 25 C) (Max) (mV) | 3 |
| Iq per channel (Typ) (mA) | 0.043 |
| Vn at 1 kHz (Typ) (nV/rtHz) | 42 |
| Rating | Catalog |
| Operating temperature range (C) | -40 to 85 |
| Offset drift (Typ) (uV/C) | 1.3 |
| Input bias current (Max) (pA) | 4 |
| CMRR (Typ) (dB) | 83 |
| Output current (Typ) (mA) | 21 |
| Architecture | CMOS |
Rail-to-rail output swing | ? |
Micropower operation (<0.5 mW) | ? |
Specified for 100 k | ? |
High voltage gain | 120 dB |
Low input offset voltage | 3 mV |
Low offset voltage drift | 1.3 μV/°C |
Ultra low input bias current | 2 fA |
Input common-mode includes GND | ? |
Operating range from +5V to +15V | ? |
Low distortion | 0.01% at 1 kHz |
Slew rate | 0.11 V/μs |
Full military temperature range available | ? |
The LPC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It features a wide range of operating voltage from +5V to +15V, rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain (into 100 k
and 5 k) are all equal to or better than widely accepted bipolar equivalents, while the power supply requirement is typically less than 0.5 mW.
This chip is built with National's advanced Double-Poly Silicon-Gate CMOS process.
See the LPC660 datasheet for a Quad CMOS operational amplifier and LPC661 for a single CMOS operational amplifier with these same features.
