具有集成 PLL 和 4 个 LVPECL 输出的 1 至 800MHz 精密时钟分配器
20 fs additive jitter Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz Clock output frequency range of 1 to 800 MHz 4 LVPECL clock outputs Dedicated divider and delay blocks on each clock output Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Data Converter Clocking Networking, SONET/SDH, DSLAM Wireless Infrastructure Medical Test and Measurement Military / Aerospace
| Function | Clock generator |
| Number of outputs | 4 |
| Output frequency (Max) (MHz) | 800 |
| Core supply voltage (V) | 3.3 |
| Output supply voltage (V) | 3.3 |
| Input type | LVCMOS, LVPECL |
| Output type | LVPECL |
| Operating temperature range (C) | -40 to 85 |
| Features | Integrated integer-N PLL, uWire |
| Rating | Catalog |
Target Applications
The
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.
