| Sample rate (Max) (MSPS) | 1000 |
| Resolution (Bits) | 8 |
| Number of input channels | 1 |
| Interface type | Parallel LVDS |
| Analog input BW (MHz) | 1700 |
| Features | Ultra High Speed |
| Rating | Catalog |
| Input range (Vp-p) | 0.8 |
| Power consumption (Typ) (mW) | 1430 |
| Architecture | Folding Interpolating |
| SNR (dB) | 48 |
| ENOB (Bits) | 7.5 |
| SFDR (dB) | 58.5 |
| Operating temperature range (C) | -40 to 85 |
| Input buffer | No |
- Internal Sample-and-Hold
- Single +1.9V ±0.1V Operation
- Adjustable Output Levels
- Ensured No Missing Codes
- Low Power Standby Mode
The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6?GSPS. Consuming a typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 500 MHz input signal and a 1?GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of a reduced common mode voltage of 0.8V.
The converter has a 1:2 demultiplexer that feeds two LVDS buses, reducing the output data rate on each bus to half the sampling rate. The data on these buses are interleaved in time to provide a 500 MHz output rate per bus and a combined output rate of 1?GSPS.
The converter typically consumes less than 10 mW in the Power Down Mode and is available in a 128-lead HLQFP and operates over the industrial (–40°C ≤ TA?≤ +85°C) temperature range.
