| Resolution (Bits) | 14 |
| Number of DAC channels (#) | 1 |
| Interface type | Parallel LVDS |
| Sample/update rate (MSPS) | 400 |
| Features | Low Power |
| Rating | Space |
| Interpolation | 1x |
| Power consumption (Typ) (mW) | 660 |
| SFDR (dB) | 82 |
| Architecture | Current Sink |
| Operating temperature range (C) | -55 to 125, 25 to 25, -55 to 115 |
| Reference type | Int |
- QMLV (QML Class V) MIL-PRF-38535 Qualified, SMD 5962-07204
- 5962-0720401VXC – Qualified over the Military Temperature Range (–55°C to 125°C)
- 5962-0720402VXC – Qualified over Reduced Temperature Range (–55°C to 115°C) for Improved Dynamic Performance
- High-Performance 52-Pin Ceramic Quad Flat Pack (HFG)
- 400-MSPS Update Rate
- LVDS-Compatible Input Interface
- Spurious-Free Dynamic Range (SFDR) to Nyquist
- 69 dBc at 70 MHz IF, 400 MSPS
- W-CDMA Adjacent Channel Power Ratio (ACPR)
- 73 dBc at 30.72 MHz IF, 122.88 MSPS
- 71 dBc at 61.44 MHz IF, 245.76 MSPS
- Differential Scalable Current Outputs: 2 to 20 mA
- On-Chip 1.2-V Reference
- Single 3.3-V Supply Operation
- Power Dissipation: 660 mW at ?CLK = 400 MSPS, ?OUT = 20 MHz
- APPLICATIONS
- Radiation Hardened Digital to Analog (DAC) Applications
- Space Satellite RF Data Transmission
- Cellular Base Transceiver Station Transmit Channel:
- CDMA: WCDMA, CDMA2000, IS-95
- TDMA: GSM, IS-136, EDGE/GPRS
- Supports Single-Carrier and Multicarrier Applications
- Engineering Evaluation (/EM) Samples are Available(1)
(1) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (for example, no burn-in) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.
All other trademarks are the property of their respective owners
The DAC5675A-SP is a radiation-tolerant, 14-bit resolution high-speed digital-to-analog converter (DAC) primarily suited for space satellite applications. The DAC5675A-SP is designed for high-speed digital data transmission in wired and wireless communication systems, high-frequency direct digital synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675A-SP has excellent SFDR at high intermediate frequencies, which makes it well suited for multicarrier transmission in TDMA and CDMA based cellular base transceiver stations (BTSs).
The DAC5675A-SP operates from a single supply voltage of 3.3 V. Power dissipation is 660 mW at ?CLK?=?400 MSPS, ?OUT = 70 MHz. The DAC5675A-SP provides a nominal full-scale differential current output of 20 mA, supporting both single-ended and differential applications. The output current can be directly fed to the load with no additional external output buffer required. The output is referred to the analog supply voltage AVDD.
The DAC5675A-SP includes a low-voltage differential signaling (LVDS) interface for high-speed digital data input. LVDS features a low differential voltage swing with a low constant power consumption across frequency, allowing for high-speed data transmission with low noise levels (low electromagnetic interference (EMI)).
LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for high-speed interfacing between the DAC5675A-SP and high-speed low-voltage CMOS ASICs or FPGAs.
The DAC5675A-SP current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered input latches provide for minimum setup and hold times, thereby relaxing interface timing.
The DAC5675A-SP is specifically designed for a differential transformer-coupled output with a 50-Ω doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to AVDD and have voltage compliance ranges from AVDD?– 1 to AVDD + 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to adjust this output current from 20 to 2 mA. This provides 20-dB gain range control capabilities. Alternatively, an external reference voltage may be applied. The DAC5675A-SP features a SLEEP mode, which reduces the standby power to approximately 18 mW.
The DAC5675A-SP is available in a 52-pin ceramic nonconductive tie-bar package (HFG). The device is specified for operation over the military temperature range of –55°C to 125°C and W temperature range of –55°C to 115°C.
