| Technology Family | AUC |
| Supply voltage (Min) (V) | 0.8 |
| Supply voltage (Max) (V) | 2.7 |
| Number of channels (#) | 8 |
| IOL (Max) (mA) | 9 |
| IOH (Max) (mA) | -9 |
| ICC (Max) (uA) | 20 |
| Input type | Standard CMOS |
| Output type | 3-State |
| Features | Balanced outputs, Ultra high speed (tpd <5ns), Partial power down (Ioff), Over-voltage tolerant inputs |
| Rating | Catalog |
- Optimized for 1.8-V Operation and is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- Ioff Supports Partial-Power-Down Mode Operation
- Sub 1-V Operable
- Max tpd of 1.7 ns at 1.8 V
- Low Power Consumption, 20-μA Max ICC
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
This octal buffer/driver is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
This device is organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
