| Number of channels (#) | 8 |
| Technology Family | LVT |
| Supply voltage (Min) (V) | 2.7 |
| Supply voltage (Max) (V) | 3.6 |
| Input type | TTL-Compatible CMOS |
| Output type | Push-Pull |
| Clock Frequency (Max) (MHz) | 150 |
| IOL (Max) (mA) | 64 |
| IOH (Max) (mA) | -32 |
| ICC (Max) (uA) | 5000 |
| Features | Ultra high speed (tpd <5ns), Over-voltage tolerant inputs, Partial power down (Ioff), Bus-hold |
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Typical VOLP (Output Ground Bounce)
???<0.8 V at VCC = 3.3 V, TA = 25°C - Supports Unregulated Battery Operation Down to 2.7 V
- Buffered Clock and Direct-Clear Inputs
- Individual Data Input to Each Flip-Flop
- Ioff Supports Partial Power-Down-Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 500 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
This octal D-type flip-flop is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct-clear (CLR)\ input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
