| Configuration | Universal |
| Bits (#) | 4 |
| Technology Family | LS |
| Supply voltage (Min) (V) | 4.5 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Bipolar |
| Output type | Push-Pull |
| Clock Frequency (MHz) | 25 |
| IOL (Max) (mA) | 8 |
| IOH (Max) (mA) | -0.4 |
| ICC (Max) (uA) | 63000 |
| Features | High speed (tpd 10-50ns) |
- Synchronous Parallel Load
- Positive-Edge-Triggered Clocking
- Parallel Inputs and Outputs from Each Flip-Flop
- Direct Overriding Clear
- J and K\ Inputs to First Stage
- Complementary Outputs from Last Stage
- For Use in High Performance:
- Accumulators/Processors
- Serial-to-Parallel, Parallel-to-Serial Converters
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These 4-bit registers feature parallel inputs, parallel outputs, J-K\ serial inputs, shift/load (SH/LD\) control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The register has two modes of operation:
Parallel (broadside) loadShift (in the direction QA toward QD)
Parallel loading is accomplished by applying the four bits of data and taking SH/LD\ low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when SH/LD\ is high. Serial data for this mode is entered at the J-K\ inputs. These inputs permit the first stage to perform as a J-K\, D-, or T-type flip-flop as shown in the function table.
The high-performance 'S195, with a 105-megahertz typical maximum shift-frequency, is particularly attractive for very-high-speed data processing systems. In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register.
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