| Number of channels (#) | 8 |
| Technology Family | ALS |
| Supply voltage (Min) (V) | 4.5 |
| Supply voltage (Max) (V) | 5.5 |
| Input type | Bipolar |
| Output type | 3-State |
| Clock Frequency (Max) (MHz) | 75 |
| IOL (Max) (mA) | 24 |
| IOH (Max) (mA) | -2.6 |
| ICC (Max) (uA) | 79000 |
| Features | High speed (tpd 10-50ns), Inverting output, Flow-through pinout |
- 3-State I/O-Type Read-Back Inputs
- Bus-Structured Pinout
- Choice of True or Inverting Logic
- SN74ALS666...True Outputs
- SN74ALS667...Inverted Outputs
- Preset and Clear Inputs
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs
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These 8-bit D-type transparent latches are designed specifically for storing the contents of the input data bus, plus reading back the stored data onto the input data bus. In addition, they provide a 3-state buffer-type output and are easily utilized in bus-structured applications.
While the latch enable (LE) is high, the Q outputs of the SN74ALS666 follow the data (D) inputs. The Q\ outputs of the SN74ALS667 provide the inverse of the data applied to its D inputs. The Q or Q\ output of both devices is in the high-impedance state if either output-enable (OE1\ or OE2\) input is at a high logic level.
Read back is provided through the read-back control (OERB\) input. When OERB\ is taken low, the data present at the output of the data latches passes back onto the input data bus. When OERB\ is taken high, the output of the data latches is isolated from the D inputs. OERB\ does not affect the internal operation of the latches; however, caution should be exercised to avoid a bus conflict.
The SN74ALS666 and SN74ALS667 are characterized for operation from 0°C to 70°C.
