单路 2 输入、0.8V 至 3.6V 低功耗或非门
| Technology Family | AUP |
| Number of channels (#) | 1 |
| Supply voltage (Min) (V) | 0.8 |
| Supply voltage (Max) (V) | 3.6 |
| Inputs per channel | 2 |
| IOL (Max) (mA) | 4 |
| IOH (Max) (mA) | -4 |
| Output type | Push-Pull |
| Input type | Standard CMOS |
| Features | Partial power down (Ioff), Over-voltage tolerant Inputs, Very high speed (tpd 5-10ns) |
| Data rate (Max) (Mbps) | 100 |
| Rating | Catalog |
- Available in the Ultra Small 0.64 mm2 Package (DPW) with 0.5-mm Pitch
- Low Static-Power Consumption
(ICC = 0.9 μA Max) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typ)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
- Input Hysteresis Allows Slow Input Transition and Better Switching-Noise Immunity at the Input
(Vhys = 250?mV Typ at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.6 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
This single 2-input positive-NOR gate performs the Boolean function Y = A + B or Y = A × B in positive logic.
