3 通道、3 输入、2V 至 5.5V 与门
| Technology Family | LV-A |
| Supply voltage (Min) (V) | 2 |
| Supply voltage (Max) (V) | 5.5 |
| Number of channels (#) | 3 |
| Inputs per channel | 3 |
| IOL (Max) (mA) | 12 |
| IOH (Max) (mA) | -12 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Partial power down (Ioff), Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) |
| Data rate (Max) (Mbps) | 70 |
| Rating | Catalog |
| Operating temperature range (C) | -40 to 85 |
- 2-V to 5.5-V VCC Operation
- Max tpd of 7 ns at 5 V
- Typical VOLP (Output Ground Bounce)
???<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
???>2.3 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
These triple 3-input positive-AND gates are designed for 2-V to 5.5-V VCC operation.
The ?LV11A devices perform the Boolean function Y = A ? B ? C or Y = (A\ + B\ + C\)\ in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
