| Technology Family | LVC |
| Applications | GPIO |
| Bits (#) | 1 |
| High input voltage (Min) (Vih) | 1.08 |
| High input voltage (Max) (Vih) | 5.5 |
| Vout (Min) (V) | 1.65 |
| Vout (Max) (V) | 5.5 |
| IOH (Max) (mA) | -32 |
| IOL (Max) (mA) | 32 |
| Rating | Catalog |
- ESD protection exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
- Available in the Texas Instruments NanoFree? package
- Fully configurable dual-rail design allows each port to operate over the full 1.65-V to 5.5-V power-supply range
- VCC isolation feature – if either VCC input is at GND, both ports are in the high-impedance state
- DIR input circuit referenced to VCCA
- Low power consumption, 4-μA maximum ICC
- ±24-mA output drive at 3.3 V
- Ioff supports partial-power-down mode operation
- Maximum data rates
- 420 Mbps (3.3-V to 5-V translation)
- 210 Mbps (translate to 3.3 V)
- 140 Mbps (translate to 2.5 V)
- 75 Mbps (translate to 1.8 V)
- Latch-up performance exceeds 100 mA per JESD 78, Class II
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry is always active on both A and B ports and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.
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