| Arm CPU | 2 Arm Cortex-A15 |
| Arm MHz (Max.) | 1800 |
| Co-processor(s) | 2 Dual Arm Cortex-M4 |
| CPU | 32-bit |
| Graphics acceleration | 1 2D, 2 3D |
| Display type | 1 HDMI, 3 LCD |
| Protocols | Ethernet |
| Ethernet MAC | 1-Port 10/100/1000, 2-Port 1Gb switch |
| PCIe | 1 PCIe Gen 2 |
| Hardware accelerators | 1 Image Video Accelerator, 1 Image Subsystem Processor, 2 Viterbi Decoder, Audio Tracking |
| Features | Multimedia |
| Operating system | Android, Linux, RTOS |
| Security | Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection |
| Rating | Automotive |
| Operating temperature range (C) | -40 to 125 |
DRA77xP 和 DRA76xP (Jacinto 6 Plus) 汽车 应用 处理器旨在满足现代车内数字驾驶舱体验对于处理性能的强烈需求。
利用该器件，原始设备制造商 (OEM) 和原始设计制造商 (ODM) 得以将创新型连接技术、语音识别和音频流式传输等快速投入实施。Jacinto 6 Plus 器件通过极其灵活的全集成混合处理器解决方案，实现了非常高的处理性能。此外，这些器件还将可编程的视频处理功能与高度集成的外设集完美融合。
其配有 Neon? 扩展的双核 Arm Cortex-A15 RISC CPU、TI C66x VLIW 浮点 DSP 内核和 Vision AccelerationPac（含一个或多个 EVE），具有可编程性。借助 Arm，开发人员能够将控制函数与在 DSP 和协处理器上编程的其他算法分离开来，从而降低系统软件的复杂性。
此外，TI 提供一整套针对 Arm、DSP 和 EVE 协处理器的开发工具，其中包括 C 语言编译器和一个可查看源代码的调试界面。
每个器件都具有加密加速特性。高安全性 (HS) 器件上还提供支持的所有其他安全 特性，包括安全引导支持、调试安全性和可信执行环境支持。有关 HS 器件的更多信息，请联系您的 TI 代表。
DRA77xP 和 DRA76xP Jacinto 6 Plus 处理器系列器件符合 AEC-Q100 标准。
DRA77x and DRA76x (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.
The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.
Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA77x and DRA76x Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.
