| Arm CPU | 1 Arm Cortex-A15 |
| Arm MHz (Max.) | 600 |
| Co-processor(s) | 2 Dual Arm Cortex-M4 |
| CPU | 32-bit |
| Graphics acceleration | 1 2D, 1 3D |
| Display type | 1 HDMI, 2 LCD |
| Protocols | Ethernet, ICSS, Profibus |
| Ethernet MAC | 1-Port 10/100/1000, 2-Port 1Gb switch |
| PCIe | 2 PCIe Gen 2 |
| Hardware accelerators | 1 Image Video Accelerator, 2 Viterbi Decoder, 1 Audio Tracking Logic |
| Features | Multimedia |
| Operating system | Android, Linux, RTOS |
| Security | Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection |
| Rating | Automotive |
| Operating temperature range (C) | -40 to 125 |
DRA71x 处理器采用 538 焊球、17mm × 17mm、0.65mm 焊球间距（0.8mm 间距规则可用于信号）球栅阵列 (BGA) 封装（采用了 Via Channel? 阵列 (VCA) 技术）。
此架构旨在通过具有成本效益的解决方案，为汽车应用提供高性能并发性 ， 从而实现 DRA75x（“Jacinto 6 EP”和“Jacinto 6 Ex”）、DRA74x“Jacinto 6”和 DRA72x“Jacinto 6 Eco”信息娱乐处理器系列的全面可扩展性，包括图像、语音、HMI、多媒体和智能手机投影模式功能。
可编程性通过具有 Arm Neon?扩展的单核 Arm Cortex-A15 RISC CPU 和 TI C66x VLIW 浮点 DSP 内核实现。借助 Arm 处理器，开发人员能够将控制函数与在 DSP 和协处理器上编程的其他算法分离开来，从而降低系统软件的复杂性。
此外，TI 提供了一整套针对 Arm 和 DSP 的开发工具，其中包括 C 语言编译器和一个可查看源代码执行情况的调试界面。
每个器件都具有加密加速特性。HS（高安全性）器件上还提供支持的所有其他安全 特性，包括安全引导支持、调试安全性和可信执行环境支持。有关 HS 器件的更多信息，请联系您的 TI 代表。
DRA71x Jacinto 6 Entry 处理器系列器件符合 AEC-Q100 标准。
该器件 采用 简化的电源轨映射，这使得低成本电源管理集成电路 (PMIC) 解决方案得以实现。
The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel? Array (VCA) technology, ball grid array (BGA) package.
The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.
Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.
Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard.
The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.
