USB 2.0 Transceiver Macrocell

High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support.For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today's gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0signaling running at hundreds of MHz, the existing design methodology must change.As operating frequencies go up it becomes more difficult to compile VHDL code without modification.This document defines the USB 2.0 Transceiver Macrocell Interface (UTMI) and many operational aspects of the USB 2.0 Transceiver Macrocell (UTM). The intent of the UTMI is to accelerate USB 2.0 peripheral development. This document defines an interface to which ASIC and peripheral vendors can develop.ASIC vendors and foundries will implement the UTM and add it to their device libraries. Peripheral and IP vendors will be able to develop their designs, insulated from the high-speed and analog circuitry issues associated with the USB 2.0 interface, thus minimizing the time and risk of their development cycles.The figure below summarizes a number of concepts expressed throughout this spec. There are assumed to be three major functional blocks in a USB 2.0 peripheral ASIC design: the USB 2.0 Transceiver Macrocell,the Serial Interface Engine (SIE), and the device specific logic.

USB 2.0 Transceiver Macrocell (UTM)
This block handles the low level USB protocol and signaling. This includes features such as; data serialization and deserialization, bit stuffing and clock recovery and synchronization. The primary focus of this block is to shift the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic in the ASIC.
Some key features of the USB 2.0 Transceiver are:
• Eliminates high speed USB 2.0 logic design for peripheral developers
• Standard Transceiver interface enables multiple IP sources for USB 2.0 SIE VHDL
• Supports 480 Mbit/s "High Speed" (HS)/ 12 Mbit/s “Full Speed” (FS), FS Only and "Low Speed" (LS)
Only 1.5 Mbit/s serial data transmission rates.
• Utilizes 8-bit parallel interface to transmit and receive USB 2.0 cable data
• SYNC/EOP generation and checking
• Allows integration of high speed components in to a single functional block as seen by the peripheral designer
• High Speed and Full Speed operation to support the development of "Dual Mode" devices
• Data and clock recovery from serial stream on the USB