Fixed Point DSP Implementation

Abstract : It has been shown earlier and rediscovered
recently that Low-Density Parity Check  Codes can
achieve bit error rate near to Shannon limit. They can
be decoded using soft decision iterative decoding
scheme. As low cost, high performance  DSPs are
widespread, DSP implementation for LDPC decoder is
a viable option. Floating point implementation has
higher costs and so fixed point DSP implementation is
considered. Various optimal and sub-optimal
implementations of the algorithm are considered.
Various algorithms are compared for performance loss
and low complexity trade off. It is shown that there is
no performance loss as compared to floating point
software approach. A lowered complexity and higher
speed implementation of the LDPC decoder can thus be
achieved using fixed point DSP implementation.