CMOS PLL Synthesizers:Analysis

In the last decade, the rapid growth of wireless applications has led to an
increasing demand of fully integrated, low-cost, low-power, and highperformance
transceivers. The applications of wireless communication
devices include pagers, cordless phones, cellular phones, global positioning
systems (GPS), and wireless local area networks (WLAN), transmitting
either voice or data. A standard specifies how devices talk to each other.
Numerous standards emerged and are optimized for certain applications. For
voice, examples include AMPS, NMT, TACS, D-AMPS, DECT, GSM,
DCS, PCS, PDC, TDMA, CDMA, etc. It has evolved from analog to digital,
from the 1G (first generation) to the current existing 2.5G, such as GPRS
and EDGE. Devices in the 3G wireless standards, which include UMTS
(WCDMA), CDMA2000 and TD-SCDMA, are also emerging in some areas
of the world. For data, there are 802.11a/b/g WLAN, HiperLAN, Bluetooth,
HomeRF, and so on. More recently, a significant interest has grown in the
ultra wideband communications [1], [2]. Figure 1-1 briefly illustrates the
frequency band of some wireless communication standards.
The recent boom of the mobile telecommunication market has driven
worldwide electronic and communication companies to produce small-size,
low-power, high-performance and certainly low-cost mobile terminals. The
current wireless transceivers involve SiGe bipolar, GaAs and CMOS
integrated RF front end and some discrete high-performance components.
From a cost of technology point of view, the standard CMOS process is the
cheapest one. With a constantly decreasing feature size, it is possible to design the radio frequency integrated circuits (RFIC) in CMOS technology.
A single-chip transceiver with a minimum number of off-chip components is
preferred to reduce the cost and size of wireless devices, like cellular phones
[3]-[7].