Parasitic-Aware Optimization o

Parasitic-Aware Optimization of CMOS RF Circuits:In the near future, people’s daily activities will be dominated with
portable wireless devices. To make compact and energy efficient mobile
communicating equipment such as mobile phones, wireless modems, twoway
radios, etc., integrated circuit technology (IC) is necessary because it
not only reduces the size, weight, and power consumption of such devices, it
enables manufacturers to include greater functionality at lower costs. Figure
1-1 shows a general system-on-chip (SOC) solution that comprises digital,
analog, micro-electro-mechanical systems (MEMS), and radio frequency
(RF) circuit blocks. By implementing a sensor in conjunction with an RF
front end, the SOC can receive or transmit data from external sources. The
digital circuitry on the chip consists of CPU, DSP, and memory blocks, and
is used for data processing. Analog-to-digital converters (ADC) and digitalto-
analog converters (DAC) enable the communication of information
between the digital and analog circuits.
It was not long ago that all RF circuits were implemented using gallium
arsenide (GaAs) or bipolar junction transistor (BJT) technologies. CMOS
technology was not viable due to its low values of breakdown voltage,
small-signal transconductance, and unity current gain frequency
Moreover, the lossy silicon substrates contributed a plethora of parasitic
elements to the monolithic passive components that made CMOS inferior to
its bipolar and GaAs counterparts.
However, because CMOS has dominated the world of digital ICs for
more than a quarter century and has achieved a very high level of integration, it has become an extremely compelling and cost effective option for use in
SOC design [1],[2]. It has been shown that mixed-signal functions such as
ADCs are effectively designed in CMOS [3],[4]. But despite a large number
of books and other publications [5]-[7], critical RF circuitry such as lownoise
amplifiers (LNA), up- and down-conversion mixers, voltagecontrolled
oscillators (VCO), power amplifiers (PA), and wide-band
amplifiers still pose difficult challenges to circuit designers. Alternative
solutions such as multi-chip modules and System-in-Package (SIP) solutions
along with the use of the traditional GaAs technology are difficult to
implement or expensive. Thus, in order to exploit CMOS as the technology
solution for high-volume SOC design and manufacture, the inferior nature of
the technology, especially with respect to parasitic elements, needs to be
overcome. Our experience over the past several years has shown that one
way to achieve high performance designs with robust manufacturing
characteristics vis-a-vis process, temperature, and voltage variations is to
perform global optimization of CMOS RF integrated circuits by including
all device and package parasitics as part of the design process.