基于Slice的总线宏的简易设计

针对传统的实现FPGA局部动态可重构中总线宏的设计方法比较复杂的问题，提出了一种Virtex-5 FPGA局部动态重构中基于Slice的总线宏的简易设计方法。在介绍总线宏基本原理的基础上，分析传统设计方法的复杂性，结合Virtex-5芯片的结构特点，以Xilinx的ISE9.1i和PlanAhead9.2.7开发软件为依托，通过宏文件获取、模块例化和连线以及放置总线宏来实现总线宏的设计。实验和仿真结果表明，该方法简单易行、灵活性强，能够工程化应用于Virtex-5 FPGA的局部动态重构设计中。

Abstract:

 Aiming at the problem that the traditional method of designing and realization the bus macro in FPGA dynamic partial reconfiguration was complicated， a facility method to design the Virtex-5 FPGA bus macro based on Slice-based was proposed. On the basis of introducing bus macro basic principle， the complexity of the traditional design methods was analyzed. Combined with the characteristic of Virtex-5 chip， relied on the Xilinx’ISE9.1i and PlanAhead9.2.7 software， the design of bus macro was realized by getting the macro file，module implement and connecting leads as well as placing the bus macro. The results of experiment and simulation show that this method is sinrple， praticable and flexible， which can be applied to Virtex-5 FPGA dynamic partial reconfiguration’s designing.