飞思卡尔SSI模块培训资料

Independent or shared transmit and receive sections with separate
or shared internal/external clocks and frame syncs, operating in
master or slave mode

Normal mode with frame sync

Network mode allowing multiple devices to share the port with as
many as 32 time slots

Gated clock mode with no frame sync
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2 sets of transmit and receive FIFOs, each is 15x32bits

Programmable data interface mode: I2S, lsb or msb-aligned

Programmable word length (8,10,12,16,18,20,22 or 24bits)

AC97 support

Transmit and receive time slot mask registers for reduced CPU
overhead