MSP430x1xx Family User's Guide

　　1.1 Architecture The MSP430 incorporates a 16-bit RISC CPU， peripherals， and a flexible clock system that interconnect using a von-Neumann common memory address bus （MAB） and memory data bus （MDB）。 Partnering a modern CPU with modular memory-mapped analog and digital peripherals， the MSP430 offers solutions for demanding mixed-signal applications. Key features of the MSP430x1xx family include： ： Ultralow-power architecture extends battery life 0.1-µA RAM retention 0.8-µA real-time clock mode 250-µA / MIPS active ： High-performance analog ideal for precision measurement 12-bit or 10-bit ADC — 200 ksps， temperature sensor， VRef 12-bit dual-DAC Comparator-gated timers for measuring resistive elements Supply voltage supervisor ： 16-bit RISC CPU enables new applications at a fraction of the code size. Large register file eliminates working file bottleneck Compact core design reduces power consumption and cost Optimized for modern high-level programming Only 27 core instructions and seven addressing modes Extensive vectored-interrupt capability ： In-system programmable Flash permits flexible code changes， field upgrades and data logging

　　1.2 Flexible Clock System The clock system is designed specifically for battery-powered applications. A low-frequency auxiliary clock （ACLK） is driven directly from a common 32-kHz watch crystal. The ACLK can be used for a background real-time clock self wake-up function. An integrated high-speed digitally controlled oscillator （DCO） can source the master clock （MCLK） used by the CPU and high-speed peripherals. By design， the DCO is active and stable in less than 6 µs. MSP430-based solutions effectively use the high-performance 16-bit RISC CPU in very short bursts. ： Low-frequency auxiliary clock = Ultralow-power stand-by mode ： High-speed master clock = High performance signal processing