倒装芯片CSP封装

芯片级封装介绍本应用笔记提供指引使用与PCB安装设备相关的芯片级封装。包括系统的PCB布局信息制造业工程师和制造工艺工艺工程师。

“包”概述

倒装芯片CSP的“包”概述半导体封装提供的芯片级封装代表最小的足迹大小，因为包是同样大小的模具。安森美半导体提供几种类型CSP。此应用笔记只涵盖那些较大焊料凸点。倒装芯片CSP凸模创建附加焊料球体到晶片的活性侧的I / O焊盘。这个I/O布局可以是外围格式，也可以是数组格式。一分配层可用于路由设备垫到凹凸垫。焊料凸点允许封装的兼容性与标准表面贴装技术连接选择并放置和回流过程和标准倒装芯片安装系统。倒装芯片的较大焊料凸点CSP无需底部填充以提高可靠性性能。焊料的铅−自由但主要共晶SnPb焊料是可用的。较小的凸块设计的设备通常有周边垫布局和紧缩间距。在这种情况下，底部填充建议提高板级焊料焊点可靠性。

Package Construction and Process Description Flip Chip CSPs are created at the wafer level. Upon completion of standard wafer processing， a polymeric Repassivation layer is applied to the wafer， leaving the bonding pads exposed. In the case where bumps are formed directly over the device bonding pads （Bump on I/O）， an under bump metallization （UBM）is applied to the bonding pads to provide an interface between the die pad metallization and the solder bump. The UBM may be a sputtered AlNiVCu thin film or an electroplate Cu. In the case where the solder bumps are offset from the device bonding pads， a plated RDL trace is applied to connect the device bonding pad to the UBM. Solder spheres are placed on each exposed UBM pad and reflowed to create an interconnection system ready for board assembly. Once the bumps are reflowed， wafers are laser marked， electrically tested， sawn into individual die， and packed in tape and reel， bumps down. A typical Flip Chip CSP is represented in Figure 1. Total device thickness varies， depending on customer requirements.