集成的DSP和RISC内核设置新的性能上限

　　集成的DSP和RISC内核设置新的性能上限

　　微控制器（MCU）解决了低端，数字信号处理（DSP）为核心的应用多年，硬件乘法累加（MAC）在数字信号控制器（DSC）单位，大大扩展了DSP的能力。不过，MCU集成的外设和存储器已经远远低于水平的专用DSP为核心处理器，微处理器，DSP核心还整合了一次了。性能的差距正在缩小，但是，随着多核MCU产品供应商如德克萨斯仪器（TI）和恩智浦半导体。让我们探索面向DSP挑战的嵌入式设计人员的最新选择，但它们也面临着系统覆盖率和功耗问题，这些问题通常会导致基于MCU的方法。

　　强大的DSP为中心的能力，MCU可以追溯到十年在这一点上的第一个电池介绍。Microchip DSC的杜撰术语dsPIC30家庭结合16位PIC24单片机硬件乘法累加（MAC）引进能力和其他DSP为核心的功能，如桶式移位器。TI走近段不同，利用处理器技术的DSP核心遗产并将其融入在C2000系列的存储器和外设的MCU架构。

　　Multi-core MCUs

　　The DSC architectures mentioned above are single-core designs whether based on an MCU or DSP legacy. The latest TI and NXP DSP-centric offerings， however， are true multi-core designs. The intent in each case is to dedicate a core to the tasks for which it is best suited.

　　TI‘s new Concerto family such as the XF28M35H52C1RFPT combines a C28x DSP-centric core， including a floating-point unit （FPU）， that is essentially evolved from the TMS320F283x Delfino MCU family with an ARM Cortex-M3 RISC core that the company has used in the StellarisMCU family. In reality， designers that utilize Concerto get two MCUs in one as depicted in the block diagram （Figure 1）。 Each core has its own dedicated set of memory and peripherals. There is also a block of shared resources that support power clock and clock distribution， and interprocessor communications， and implement basic analog peripherals.