实时：关于微控制器中断等待时间的一些注释

　　实时：关于微控制器中断等待时间的一些注释

　　中断需要大量的高速处理器，特别是大量流水线的处理器，每个周期能够发出多条指令。在任何一次飞行中都可能有八到十个指令，要么必须运行到完成，要么在正常执行恢复后取消并重新启动。

　　电气工程师需要检查中断对应用程序的响应是否足够快，并且中断的开销不会淹没主应用程序。

　　一个给定的MCU执行中断的速度有多快？这肯定会受到应用程序的影响，但是对于这个项目来说，找到一个数字似乎是不合理的。

　　当中断发生时，CPU保存一些寄存器并执行中断服务例程（ISR），然后返回就绪状态中的最高优先级任务。中断通常屏蔽和嵌套。

　　明确地说，延迟通常被指定为中断请求和中断服务例程中第一个指令的执行之间的时间。然而，“真正的延迟”必须包括一些必须在ISR中完成的内务处理，这会导致混乱。

　　The value in which an electrical engineer is usually interested is the worst -case interrupt latency. This is a sum of many different smaller delays.

　　The interrupt request signal needs to be synchronized to the CPU clock. Depending on the synchronization logic， typically up to three CPU cycles can be lost before the interrupt request has reached the CPU core.

　　The CPU will typically complete the current instruction. This instruction can take a lot of cycles， with divide， push-multiple， or memory-copy instructions requiring most clock cycles taking the most time. There are often additional cycles required for memory access. In an ARM7 system， for example， the instruction STMDB SP！，{R0-R11，LR} （Push parameters and perm.） Registers is typically the worst case instruction. It stores 13 32-bit registers on the stack and requires 15 clock cycles.

　　The memory system may require additional cycles for wait states.

　　After completion of the current instruction， the CPU performs a mode switch or pushes registers （typically PC and flag registers） on the stack. In general， modern CPUs （such as ARM） perform a mode switch， which requires less CPU cycles than saving registers.

　　If your CPU is pipelined， the mode switch has flushed the pipeline and a few more cycles are required to refill it. But we are not done yet. In more complex systems， there can be additional causes for interrupt latencies.