mpc5674f单片机数据表

　　• Dual issue， 32-bit CPU core complex （e200z7） – Compliant with the Power Architecture® embedded category – 16 KB I-Cache and 16 KB D-Cache – Includes an instruction set enhancement allowing variable length encoding （VLE）， optional encoding of mixed 16-bit and 32-bit instructions， for code size footprint reduction – Includes signal processing extension （SPE2） instruction support for digital signal processing （DSP） and single-precision floating point operations • 4 MB on-chip flash – Supports read during program and erase operations， and multiple blocks allowing EEPROM emulation • 256 KB on-chip general-purpose SRAM including 32 KB of standby RAM • Two direct memory access controller （eDMA2） blocks – One supporting 64 channels – One supporting 32 channels • Interrupt controller （INTC） • Frequency modulated phase-locked loop （FMPLL） • Crossbar switch architecture for concurrent access to peripherals， flash， or RAM from multiple bus masters • External bus interface （EBI） for calibration and application development （not available on all packages） • System integration unit （SIU） • Error correction status module （ECSM） • Boot assist module （BAM） supports serial bootload via CAN or SCI • Two second-generation enhanced time processor units （eTPU2） that share code and data RAM. – 32 standard channels per eTPU2 – 24 KB code RAM – 6 KB parameter （data） RAM • Enhanced modular input output system supporting 32 unified channels （eMIOS） with each channel capable of