CPU Design - Answers to Frequently Asked Questions

I am honored to write the foreword for Chandra Thimmannagari’s book on CPU
design. Chandra’s book provides a practical overview of Microprocessor and high
end ASIC design as practiced today. It is a valuable addition to the literature on CPU
design, and is made possible by Chandra’s unique combination of extensive hands-on
CPU design experience at companies such as AMD and Sun Microsystems and a
passion for writing.
Technical books related to CPU design are almost always written by researchers in
academia or industry and tend to pick one area, CPU architecture/Bus architecture/
CMOS design that is the area of expertise of the author, and present that in great
detail. Such books are of great value to students and practitioners in that area.
However, engineers working on CPU design need to develop an understanding of
areas outside their own to be effective. CPU design is a multi dimensional problem
and one dimensional optimization is often counterproductive.
For instance, as someone who mainly does CPU architecture, I have found that CPU
architects who understand how logic design, circuit design and chip integration are
really done in practice do a much better job architecting the chip. There are
constraints in these different areas that could make an architectural idea hard to
implement, and an architect who understands these constraints is more likely to make
the right decisions upfront. However, there are really no books out there to help an
architect understand quickly how the later stages of chip design work. Reading
detailed technical books on physical design to obtain this knowledge is typically not
an option given time constraints. The most accessible way today to learn the broader
skill set necessary is from chatting with friends and picking up bits of knowledge
here and there. Over time the good ones do develop a working knowledge of all areas
of CPU design, but it takes many years.
The same goes for circuit designers who want to understand architecture. I have had
several circuit engineers come to me wanting to know more about architecture. I
answer questions as time permits and suggest they read “Hennessy and Patterson”. Ithelps, but goes only so far even though H&P is a really well written book. There is
just too much detail, and it is hard to filter out what is relevant.
In a way Chandra’s book is structured as a chat with a knowledgeable friend with
much time to spare. So we could imagine a circuit designer who is working on a
cache, and has a design problem - for instance, the replacement algorithm he is trying
to implement is not making timing. He will have to discuss this with the logic owner
or architect, but it will help if he has an understanding of the architectural options
available and any potential circuit issues with those options prior to the discussion.
He could look up this book and starting with the first question on caches (Q5 in
Architecture: What is cache memory in a CPU and what are the most common terms
associated with caches?) work through replacement policy related questions (Q10 to
Q15 in Architecture) to develop an understanding of the options available. Or
imagine an architect who is told that the particular idea she has in mind cannot be
implemented owing to routing density issues related to noise. She could look up the
relevant question in the book (Q6 in Circuits and Layout: What do you mean by
effect of noise in a design and what are the most common techniques used to reduce
its effect?) to develop a quick understanding of noise issues as well as possible
solutions and work with designers to find a way to implement her idea.
The book also provides excellent lists of techniques in the experienced logic/circuit
designer’s toolbox to attack a problem. For instance, a logic designer who is trying to
figure out how to make timing for a block could go straight to Q4 in the Logic
chapter and look at the list of suggestions there for fixing timing paths and start
making headway. Or a designer who is trying to reduce power for a block or a chip
could go to Q6 in the Logic chapter and look at the list of suggestions there for
reducing power. Or a circuit designer who is trying to fix noise problems could go to
Q6 in the Circuits and Layout chapter. Or a manager who wants to learn about design
tools available for a particular task could go to the relevant question in the Tools
chapter.
The book also includes good, concise descriptions of many thorny issues in CPU
design such as RAS, electromigration, IR drop, pass gate muxes and mintime fixes.
I believe the book will be a valuable addition to any CPU designer’s library.