640主板的2048位可编程LDPC码解码芯片

WITH sustained growth in demands for multimedia,
wireless, and broadband services, significant effort has
been made to apply iterative forward error correction (FEC)
coding techniques to advanced communications systems. These
techniques have proved to be very effective in extending the
limits and services of wireless communications, expanding the
areal density of magnetic recording systems, and improving
the throughput of terrestrial optical systems. Low-density
parity-check (LDPC) codes [1] have emerged as one of the top
contenders for such applications after their main rivals, turbo
codes [2], have seen limited acceptance (particularly in optical
applications) due to their high implementation complexity,
decoding latency, as well as performance degradation for relatively
short block-length and error-floors at high signal-to-noise
ratios (SNRs). Research has shown that LDPC codes can
achieve record-breaking performance for low SNR applications
[3], [4], and are more amenable to rigorous analysis and design.
They offer more flexibility in the choice of code parameters,
and their decoders require simpler processing. These characteristics
have made it possible to design appropriate LDPC codes
for many communications scenarios; they have been adopted
in next generation digital video broadcasting (DVB-S2) via
satellite [5], and considered for adoption in wireless local
area network (WLAN) air interface (802.11) [6], wireless personal
area networks (WPANs) (802.12) [7], mobile broadband
wireless access (MBWA) networks (802.20) [8], advanced
magnetic and magneto-optic storage/recording systems [9], and
long-haul optical communication systems [10].