A Parallel LSI Architecture fo

Low-Density Parity-Check (LDPC) code achieves informa-tion rates close to the Shannon limit by using the iterative decoding algorithm called message-passing algorithm. Some work has been done on designing LDPC decoder in Refs.[2]-[6]. LDPC decoders are composed of a check functional unit (CFU) and a bit functional unit (BFU), where the CFU performs row operations and the BFU performs column opera-
tions. The message-passing algorithm exchanges the messages between the check and bit nodes iteratively.
The requirements to improve the decoding throughput and bit error performance of the LDPC decoder are as follows:(1) The single iterative decoding delay should be reduced by performing the row and column operations in parallel.(2) The number of iterations until the decoding convergence is reached should be reduced by improving the message-passing efficiency. The requirements (1) and (2) depend on the design point of view, (3) the message-passing schedule should not partition the memory into a large number of memory banks messagesince presence of a large number of memory banks makes layouts of VLSI circuit difficult [7].