实现低密度奇偶校验码的硬件结构

Low-density parity-check (LDPC) codes [1] have been
recently shown to allow communications systems to perform
close to the channel capacity limit. High data rate systems
using these codes must use dedicated hardware for LDPC
decoders. However, this hardware can be quite complex,
requiring large silicon area, and are normally power-hungry
and throughput limited. In addition, an extra challenge is to
build an efficient hardware implementation that is also flexible
for variable code rates and block sizes.
To meet these challenges, there has recently been much
work done on the study of constructions of LDPC codes with
advantages in hardware implementation. Kou, Fossorier and
Lin [2] recognized that LDPC encoding can be simplified for
codes constructed on finite geometries. Yeo et. al. [3] used the
same construction with a modified decoding schedule to
significantly reduce the decoder complexity. Zhang and Parhi
[4] and Mansour and Shanbhag [5], [6] demonstrated that the
decoder can be simplified for regular codes based on
algebraically constructed Ramanujan graphs. Hocevar [7]
showed a flexible hardware implementation of a code based on
permutation matrices.
This paper studies LDPC codes and proposes a code
construction that produces codes with properties favoring
hardware implementation along with good BER performance
with low error floors. The structure of this proposed
construction can be exploited in several ways for different
architectures supporting various degrees of flexibility and
throughput. For fully-parallel, very high throughput decoders,
these codes can reduce the amount of routing, making this a
more feasible option for blocks sizes up to 1024 bits. In
addition, these codes allow partially-serial, flexible
architectures with increased efficiency and relatilvey high
throughputs.