MCF5282 pdf

MCF5282 System Overview

MCF5282 November 2002
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product or service names are the property of their respective owners. © Motorola, Inc. 2001.

Features
􀂋ColdFireV2 core
􀂋59 Dhrystone 2.1 MIPS at 66 MHz
􀂋Enhanced MAC Module
􀂋HW Divide
􀂋Integrated Memory
􀂋2K I-cache (* for off chip accesses only)
􀂋64K RAM
􀂋512K Flash (10K W/E cycles, 10 years data retention)
􀂋0K Flash on MCF5280
􀂋Integrated Peripherals
􀂋10/100 Ethernet MAC (external PHY)
􀂋Enhanced CAN 2.0B Controller (FlexCAN)
􀂋3 UARTs (2 with flow control)
􀂋Queued Serial Peripheral Interface (QSPI)
􀂋I2C bus interface
􀂋8 ch. 16-Bit Capture/Compare/PWM timers
􀂋4 ch. 32-bit timers with DMA
􀂋8 ch. Queued 10-bit A-to-D converter
􀂋4 ch. DMA controller
􀂋SDRAM Controller
􀂋32-bit non-multiplexed data bus w/7 Chip Selects
􀂋Up to 152 General-Purpose I/O
􀂋System Integration (PLL, SW Watchdog)
􀂋Reset controller with “Brown-out” detection