74HC4514 pdf datasheet

MM54HC4514/MM74HC4514
4-to-16 Line Decoder with Latch
General Description
This utilizes advanced silicon-gate CMOS technology, which
is well suited to memory address decoding or data routing
application. It possesses high noise immunity and low power
dissipation usually associated with CMOS circuitry, yet
speeds comparable to low power Schottky TTL circuits. It
can drive up to 10 LS-TTL loads.
The MM54HC4514/MM74HC4514 contain a 4-to-16 line
decoder and a 4-bit latch. The latch can store the data on
the select inputs, thus allowing a selected output to remain
high even though the select data has changed. When the
LATCH ENABLE input to the latches is high the outputs will
change with the inputs. When LATCH ENABLE goes low
the data on the select inputs is stored in the latches. The
four select inputs determine which output will go high provided
the INHIBIT input is low. If the INHIBIT input is high all
outputs are held low thus disabling the decoder.
The MM54HC4514/MM74HC4514 is functionally and pinout
equivalent to the CD4514BM/CD4514BC and the
MC1451BA/MC1451BC. All inputs are protected against
damage due to static discharge diodes from VCC and
ground.