74LS109/54LS109 pdf datasheet

54LS109/DM54LS109A/DM74LS109A
Dual Positive-Edge-Triggered J-K Flip-Flops
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent positive-edge-triggered
J-K flip-flops with complementary outputs. The J and
K data is accepted by the flip-flop on the rising edge of the
clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of
the clock. The data on the J and K inputs may be changed
while the clock is high or low as long as setup and hold
times are not violated. A low logic level on the preset or
clear inputs will set or reset the outputs regardless of the
logic levels of the other inputs.
Features
Y Alternate Military/Aerospace device (54LS109) is available.
Contact a National Semiconductor Sales Office/
Distributor for specifications