PEX8608 pdf datasheet

The ExpressLane™ PEX 8608 device offers 8 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 8 flexible ports. The switch conforms to the PCI Express Base Specification, rev 2.0. The PEX 8608 architecture supports packet cut-thru with the industry's lowest latency of 140ns (x4 to x1) and offers two virtual channels for traffic prioritization in the system. This, combined with large packet memory (2048 byte maximum payload size) and non-blocking internal switch architecture, provide full line-rate on all ports. The PEX 8608 supports both host-centric as well as true peer-to-peer traffic. The PEX 8608 also features an on-chip Non-Transparent port for dual-host and failover applications and supports dual-clock domain operation by virtue of support for Spread Spectrum Clock (SSC) isolation. This switch is hardware configurable and software programmable, allowing users to tailor their port configurations and quality-of-service system needs to suit their application requirements. This device can be used in a wide variety of applications including control planes in the communications and networking markets, intelligent adapter cards and embedded systems. The PEX 8608 is offered in a 15 x 15mm 196-ball PBGA and is available in both leaded and lead-free packaging.