dm9000a pdf,dm9000a datasheet

Integrated 10/100M transceiver with auto-MDIX
■ System clock up to 100 MHz
■ IP/TCP/UDP checksum generation and checking
■ Up to 23 GPIO pins
■ MII and reverses MII interface
■ Supports early Tx
■ Build in 3.3V to 2.5V regulator
■ Processor interface: Byte/word/Dword
of I/O command to internal memory data operation

■ Supports back pressure mode for half-duplex mode flow control
■ IEEE802.3x flow control for full-duplex mode
■ Supports wakeup frame, link status change and
magic packet events for remote wake up
■ Integrated 4K Dword SRAM
■ Supports automatically load vendor ID and product ID from EEPROM
■ Optional EEPROM configuration
■ Very low power consumption mode:
Power reduced mode (cable detection)
Power down mode
Selectable TX drivers for 1:1 or 1.25:1 transformers
■ Compatible with 3.3V and 5.0V tolerant I/O