AD8321,pdf datasheet ( CATV Li

The attenuation setting in the AD8321 is determined by the 8-bit word in the data latch. The SDATA load sequence is initiated by a falling edge on DATEN. The gain control data (SDATA) is serially loaded (MSB first) into the 7-bit shift register at each rising edge of the clock. See Figure 24. While DATEN is low, the data latch holds the previous data word allowing the attenuation level to remain unchanged. After eight clock cycles the new data word is fully loaded and DATEN is switched high. This enables the data latch and the loaded register data is passed to the attenuator with the updated gain value. Also at this DATEN transition, the internal clock is disabled, thus inhibiting new serial input data.
The power amplifier has two basic modes of operation. A forward mode (or power-up mode) and a reverse mode (or power-down) mode. In the power-up mode (PD = 1), the power amplifier stage is enabled and the AD8321 has a maximum gain of 20 V/V or 26 dB (into 75 W). With a total attenuation of
53.43 dB in the DAC, vernier and preamp, the AD8321’s total gain range is 26 dB to –27.43 dB. In both the forward or reverse mode the single-ended output signal maintains a dc level of VCC/2. This dc output level provides for optimum large signal linearity.
In the power-down mode (PD = 0), the power amplifier is turned off and a “reverse” amplifier (the inner triangle in Figure 22) is enabled. During this 1-to-0 transition, the output power is disabled. This assures that S11 and S22 remain approximately equal to zero thus minimizing line reflections. In the time domain, as PD switches states, a transitional glitch and pedestal offset results (See Figures 14 and 15). These anomalies have been minimized by temperature compensated internal circuitry and laser trimming. The powered down supply current drops to 52 mA versus 90 mA in the power-up mode.