MAX3892,pdf,2.5Gbps/2.7Gbps, S

The MAX3892 serializer is ideal for converting 4-bit-wide, 622Mbps parallel data to 2.5Gbps serial data in DWDM and SONET/SDH applications. A 4 x 4-bit FIFO allows for any static delay between the parallel output clock and parallel input clock. Delay variation up to a unit interval (UI) is allowed after reset. A fully integrated phase-locked loop (PLL) synthesizes an internal 2.5GHz serial clock from a 622MHz, 155.5MHz, 77.8MHz, or 38.9MHz reference clock. A selectable dual VCO allows excellent jitter performance at both SONET and forward-error correction (FEC) data rates.

Operating from a single 3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (CML) serial data and clock outputs. A loopback data output is provided to facilitate system diagnostic testing. The MAX3892 is available in the extended temperature range (-40°C to +85°C) in 44-pin QFN and TQFN packages.