SN65LVDS310,pdf(Programmable 2

The SN65LVDS310 receiver deserializes FlatLink 3G-compliant serial input data to 27 parallel data outputs. The SN65LVDS310 receiver contains one shift register to load 30 bits from one serial input and latches the 24 pixel bits and 3 control bits out to the parallel CMOS outputs after checking the parity bit. If a parity error is detected, the data output bus disregards the newly received pixel. Instead, the last data word is held on the output bus for another clock cycle.

The serial data and clock are received via sub-low-voltage differential signalling (SubLVDS) lines. The SN65LVDS310 supports three operating power modes (shutdown, standby, and active) to conserve power.

When receiving, the PLL locks to the incoming clock, CLK, and generates an internal high-speed clock at the line rate of the data lines.