Ethernet IP core(Verilog)

1 ...................................................................................................................................................... 1
INTRODUCTION............................................................................................................................. 1
1.1 ETHERNET IP CORE INTRODUCTION.............................................................................. 1
1.2 ETHERNET IP CORE FEATURES...................................................................................... 1
1.3 ETHERNET IP CORE DIRECTORY STRUCTURE............................................................. 3
2 ...................................................................................................................................................... 5
ETHERNET MAC IP CORE............................................................................................................. 5
2.1 OVERVIEW .................................................................................................................... 5
2.1.1 WISHBONE Interface ................................................................................................... 5
2.1.2 Transmit Module .......................................................................................................... 5
2.1.3 Receive Module............................................................................................................ 6
2.1.4 Control Module............................................................................................................. 6
2.1.5 MII Module (Media Independent Module)................................................................... 6
2.1.6 Status Module .............................................................................................................. 6
2.1.7 Register Module........................................................................................................... 6
2.2 CORE FILE HIERARCHY .............................................................................................. 6
2.3 DESCRIPTION OF CORE MODULES........................................................................... 8
2.3.1 Description of the MII module (eth_miim.v) ............................................................ 10
2.3.2 Description of the Receive module (eth_rxethmac.v)............................................ 12
2.3.3 Description of the Transmit module (eth_txethmac.v) .......................................... 17
2.3.4 Description of the Control module (eth_maccontrol.v) ......................................... 22
2.3.5 Description of the Status module (eth_macstatus.v)............................................. 24
2.3.6 Description of the Registers module (eth_registers.v).......................................... 27
2.3.7 Description of the WISHBONE interface module (eth_wishbone.v)..................... 28