FPGA核心部分源码

FPGA核心部分源码:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;

ENTITY sbq IS
PORT (sysclk,tset,tctrl,sxin,dccf,chf,cc,xs,kz: in std_logic;
 jzclk,sxout,sxfko,ctrlnclk:out std_logic;
 ctrlclk:buffer std_logic;
 din:in std_logic_vector (7 downto 0);
 do,rdadd:out STD_LOGIC_VECTOR (7 DOWNTO 0) ); 
END sbq;

architecture sbq of sbq is
 type ram is array(255 downto 0) of std_logic_vector(7 downto 0);
 signal  dualram,dualram1 :      ram;
-- signal  dualram,dualram1 :array(255 downto 0) of std_logic_vector(7 downto 0);
 signal ct0,ct2,ct3,ct4,ct5,cnt6,ct6:std_logic;
 signal wrclk,rdclk: std_logic;
 signal wable,wable1: std_logic;
 signal dout,dout1: STD_LOGIC_VECTOR (7 DOWNTO 0);
 signal wadd,radd,wadd1:std_logic_vector(7 downto 0);
 signal wdc,wctrl,wctrl1,wdc1:std_logic;
 signal cnt0:std_logic_vector(3 downto 0);
 signal cnt5:std_logic_vector(3 downto 0);
 signal cnt1:std_logic_vector(5 downto 0);
 signal cnt2:std_logic_vector(6 downto 0);
 signal cnt3:std_logic_vector(3 downto 0);
 signal cnt4:std_logic_vector(7 downto 0);
 signal sxc:std_logic_vector(3 downto 0);
 signal sxfk:std_logic;