Designing a High Performance S

Designing a High Performance SDRAM Controller Using ispMACH Devices

Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and the ability to randomly change column addresses on each clock cycle during a burst
cycle.
This reference design provides the user with a baseline SDRAM Controller design. The user may modify the design to meet specific design requirements. This document provides information on how this design operates and shows the user where changes can be made to support other functionality.
The design was implemented in Verilog, synthesized and fitted using ispDesignEXPERT™ software into a ispMACH™ 4A device. The design requires 57 macrocells and 59 I/O pins. Using an M4A-128/64-7 yields a maximum
operating frequency of 111MHz. Using an M4A-128/64-55 yields a maximum operating frequency of 153MHz. Results may vary according to the synthesis tool.
This design assumes the reader has experience implementing page mode DRAM systems. Information available in documents listed in the Applicable Documents section is not repeated in this document.
Applicable Documents
• Micron Synchronous DRAM Data Sheet: MT48LC16M4A2/8M8A2/4M16A2
• Targeting MACH Devices Using Synplicity’s Synplify v5.0.8 with DesignDirect-Software v1.0 Application
Note
• Targeting MACH Devices Using Exemplar’s Leonardo Spectrum v1998.2d with DesignDirect Software v1.0
Application Note
Theory of Operation
Overview
This SDRAM Controller is designed to interface to standard microprocessors. The controller is independent of processor type. This design, as implemented, supports two 16MB memory regions configured as 4 M x 32 bits. Each region consists of two Micron MT48LC4M16A2 devices. Changing byte enable inputs and address inputs will change the width and size of this design. For example, if a 64-bit wide data bus is desired, increase the byte enable signals from 4 to 8. If a larger memory space is required, add address inputs and reconfigure the row and column address appropriately or add more chip selects.