SDR SDRAM Controller

SDR SDRAM Controller

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.
However, for other applications, the system designer must design a controller to provide proper commands for SDRAM initialization, read/write accesses and memory refresh. In some cases, SDRAM is chosen because the previous generations of DRAM (FP and EDO) are either end-of-life or not recommended for new designs by the memory vendors. From the board design point of view, design using earlier generations of DRAM is much easier and more straightforward than using SDRAM unless the system bus master provides the SDRAM interface module as mentioned above. This SDRAM controller reference design, located between the SDRAM and the bus master,reduces the user’s effort to deal with the SDRAM command interface by providing a simple generic system interface to the bus master. Figure 1 shows the relationship of the controller between the bus master and SDRAM. The bus master can be either a microprocessor or a user’s proprietary module interface.In today's SDRAM market, there are two major types of SDRAM distinguished by their data transfer rates. The most common single data rate (SDR) SDRAM transfers data on the rising edge of the clock. The other is the double data rate (DDR) SDRAM which transfers data on both the rising and falling edge to double the data transfer throughput. Other than the data transfer phase, the different power-on initialization and mode register definitions,these two SDRAMs share the same command set and basic design concepts. This reference design is targeted for SDR SDRAM, however, due to the similarity of SDR and DDR SDRAM, this design can also be modified for a DDR SDRAM controller. For illustration purposes, the Micron SDR SDRAM MT48LC32M4A2 (8Meg x 4 x 4 banks) is chosen for this design. Also, this design has been verified by using Micron’s simulation model. It is highly recommended to download the simulation model from the SDRAM vendors for timing simulation when any modifications are made to this design.